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Vending-machine
- Vending machine based on verilog.
verilog-ieee
- The Verilog ¤ Hardware Descr iption Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it
sell-machine
- verilog sell machine 通过robei和vivado设计的建议xilinx测试程序,有助于学习vivado和fpga-verilog vivado xilinx
shouhuojixi1
- 自动邮票售货机,选择要购买的邮票,直接投入硬币就可以购买。(Automatic stamp vending machine, select the stamps to buy, directly into coins can buy.)
4LED
- 4LED流水灯程序,可更换频率,采用状态机,低电平有效亮灯,高电平熄灭(4LED water lamp program, you can change the frequency. Using state machine, low level active light, high level extinction)
verilog_curr_design
- 基于Verilog的乒乓球游戏机,由按键代替发接球(Table tennis game machine based on Verilog language, using the buttons to serve and catch..)
control_s
- 数控机床 多轴插补原理积分算法,实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)
SEQ_DETECTOR
- 这是一个四位串行数据检测器,一共有三种模式可以选择:递增(检测连续四位递增序列),递减(检测连续四位递减序列)和不变(检测连续四位不变序列)。整个设计采用同步时钟,异步复位,用米利状态机,并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)
game
- (1)设计一个由甲、乙双方参赛,有裁判的 3 人乒乓球游戏机。 (2)用 8 个(或更多个)LED 排成一条直线,以中点为界,两边各代表参赛双方的位置,其中一只点亮的 LED 指示球的当前位置,点亮的 LED 依此从左到右,或从右到左,其移动的速度应能调节。 (3)当“球”(点亮的那只 LED)运动到某方的最后一位时,参赛者应能果断地按下位于自己一方的按钮开关,即表示启动球拍击球。若击中,则球向相反方向移动;若未击中,则对方得 1 分。 (4)一方得分时,电路自动响铃 3s,这期间发球
基于FPGA的自动售货机毕业设计
- 基于FPGA的自动售货机,采用quartus 2 编写,方便可用(Vending machine based on FPGA)
fsm
- 有限状态机fsm 二段式编写 verilog(Finite state machine, FSM, two sections, verilog)
sdram_ip
- 完成SDRAM的上电配置,状态机编写其读写模块,存储模块,并通过两个异步作为存储和读取的通道(Complete the SDRAM power-on configuration, the state machine to write its read-write module, memory module, and through two asynchronous as a storage and read the channel)
Mealy_TrafficLight
- 基于FPGA交通控制器的Mealy状态机实现(Mealy state machine controller based on FPGA traffic)
FiniteStateMachine
- 一个可以识别正则表达式的状态机,采用了多种Case描述,方便修改(A finite state machine designed for identifying expression patterns)
状态机
- 本代码跟据状态转移图,通过verilog实现了一个有限状态机。(This code implements a finite state machine with the state transition graph through verilog.)
lowpower
- 最大公约数(GCD)stein算法实现,低功耗状态机实现(The greatest common divisor (GCD) stein algorithm, low power state machine implementation)
状态机
- 设计一个简单的数字电路用于电子卖报机,要求如下: 报纸价格为1.5元;投币器只接受5角和1元硬币;投币器不找零。当投入金额合适时,报纸出口打开,否则关闭。用Verilog完成设计。(The design of a simple digital circuit for electronic selling machine, the following: The price is 1.5 yuan; the coin only accept 5 cents and $1 coin coin do
fsm3
- verilog状态机实验,说明一个状态机的生成过程(Verilog state machine experiment, which illustrates the generation process of a state machine)
信号分析与处理——MATLAB语.part1
- ① Verilog的抽象级别 ② Verilog的模块化设计 ③ 如何给端口选择正确的数据类型 ④ Verilog语言中latch的产生 ⑤ 组合逻辑反馈环 ⑥ 阻塞赋值与非阻塞赋值的不同 ⑦ FPGA的灵魂状态机 ⑧ 代码风格的重要性((1) the abstract level of Verilog The modular design of Verilog How to select the correct data type for the
segment_test
- 在verilog下设计的自动贩卖机,有数码管显示界面,有自动找零功能(The vending machine in the Verilog design, a digital display interface, automatic change function)